1. Field of the Invention
The present invention relates to a silicon-on-insulator (SOI) substrate. The present invention also relates to a semiconductor device manufactured using the SOI substrate.
2. Description of the Related Art
Recently, integrated circuits using an SOI (Silicon on Insulator) substrate where a thin single crystal semiconductor layer is formed on an insulating surface, instead of bulk-like silicon wafers, have been developed. Since parasitic capacitance between a drain of a transistor and a substrate is reduced by using the SOI substrate, the SOI substrate has attracted attention as one improving performance of semiconductor integrated circuits.
A Smart Cut method is known as one of methods for manufacturing an SOI substrate. An outline method for manufacturing an SOI substrate by a Smart Cut method is described below. First, hydrogen ions are implanted into a silicon wafer by an ion implantation method so that an ion implantation layer is formed at a predetermined depth from a surface. Next, the silicon wafer into which the hydrogen ions are implanted is bonded to another silicon wafer with a silicon oxide film interposed therebetween. After that, the ion implantation layer becomes a cleavage plane by performing heat treatment, and the wafer into which the hydrogen ions are implanted is separated into a thin film state, whereby a silicon film can be formed over the bonded silicon wafer. A Smart Cut method may be referred to as a hydrogen ion implantation separation method.
In a hydrogen ion implantation separation method, ions are separated by mass and then electromagnetically deflected to scan (raster scan) a fixed substrate, whereby ion implantation is performed. Therefore, concentration distribution of hydrogen atoms included on a surface of a semiconductor substrate varies depending on locations, and projections and depressions are generated on a surface of a cleaved silicon film. When a gate insulating film is formed over the silicon film whose surface has large projections and depressions, the projections and depressions penetrate the gate insulating film, causing a problem of leakage between a semiconductor layer and a gate electrode.
Accordingly, Chemical Mechanical Polishing (CMP) is performed on the surface of the silicon film with projections and depressions generally after cleavage. Further, a technique in which the surface of the silicon film is flattened by performing heat treatment in the hydrogen atmosphere after cleavage is disclosed in Reference 1 (Japanese Published Patent Application No. H11-307472).
Furthermore, as an example of a technique in which a single crystal silicon thin film is formed over a glass substrate by such Smart Cut, a technique by the present applicant has been known (for example, Reference 2: Japanese Published Patent Application No. H11-163363).